Fu-Liang YANG 楊富量
Distinguished Research Fellow

Ways to contact me:

Fax: 02-2787-3122
Address: Research Center for Applied Sciences, Academia Sinica
128 Sec. 2, Academia Rd., Nankang, Taipei 11529, Taiwan



Research Fields:

  • High Sensitivity and/or Rapid Identification with Nano Device for Bio-Sensor.
  • Sub-10nm CMOS Logic Device, Physics and Process Integration.
  • High Speed Low Power SRAM Cell Device, Architecture Optimization and Cell Size Minimization.
  • Integrated High Performance Energy Harvesting Chip with CMOS Device.

Recent Publications:

  1. Y.T. Tang, K.S. Li, L.J. Li, M.Y. Li, C.H. Lin, Y.-J. Chen, C.C. Chen, C.J. Su, B.W. Wu , C.S. Wu, M.C. Chen, J.M. Shieh, W.K. Yeh, P.C. Su, T. Wang, F.L. Yang , Chenming Hu , “A Numerical Study of Si-TMD Contact with n/p Type Operation and Interface Barrier Reduction for Sub-5 nm Monolayer MoS2 FET”International Electron Devices Meeting (IEDM)2016, San Francisco, USA
  2. M.C. Chen, K.S. Li, L.J. Li, M.Y. Li, Y.H. Chang, C.H. Lin, Y.-J. Chen, C.C. Chen, B.W. Wu, C.S. Wu, Y.J. Lee, J.M. Shieh, W.K. Yeh, P.C. Su, T. Wang, F.L. Yang, and Chenming Hu“Stackable MoS2 FinFETs Using Solid CVD Developed Through Fully CMOS-Compatible Process Technology”,International Conference on Solid State Devices and Materials (SSDM)2016, Tsukuba, Japan
  3. Kai-Shin Li, Bo-Wei Wu1, Lain-Jong Li, Ming-Yang Li,Chia-Chin, Kevin Cheng, Cho-Lun Hsu, Chang-Hsien Lin, Yi-Ju Chen, Chun-Chi Chen, Chien-Ting Wu, Min-Cheng Chen, Jia-Min Shieh, Wen-Kuan Yeh, Yu-Lun Chueh, Fu-Liang Yang, and Chenming Hu “MoS2 U-shape pMOSFET with 10 nm Channel Length and Doped Poly-Si Source/Drain Serving as Seed for Full Wafer CVD MoS2 Availability” IEEE Symposium on VLSI Technology (VLSI Technology), June 2016 ,Honolulu, HI, USA
  4. Min-Cheng Chen, Kai-Shin Li, Lain-Jong Li, Ang-Yu Lu, Ming-Yang Li, Yung-Huang Chang, Chang-Hsien Lin, Yi-Ju Chen, Yun-Fang Hou, Chun-Chi Chen, Bo-Wei Wu, Cheng-San Wu, Ivy Yang, Yao-Jen Lee, Jia-Min Shieh, Wen-Kuan Yeh, Jyun-Hong Shih, Po-Cheng Su, Angada B. Sachid, Tahui Wang, Fu-Liang Yang, and Chenming Hu,“TMD FinFET with 4 nm Thin Body and Back Gate Control for Future Low Power Technology” , International Electron Devices Meeting (IEDM)2015, Washington DC, USA
  5. Tsung-Ta Wu, Chang-Hong Shen*, Jia-Min Shieh*, Wen-Hsien Huang, Hsing-Hsiang Wang, Fu-Kuo Hsueh, Hisu-Chih Chen, Chih-Chao Yang, Tung-Ying Hsieh, Bo-Yuan Chen, Yu-Shao Shiao, Chao-Shun Yang, Guo-Wei Huang, Kai-Shin Li, Ting-Jen Hsueh, Chien-Fu Chen, Wei-Hao Chen, Fu-Liang Yang, Meng-Fan Chang and Wen-Kuan Yeh, “Low-Cost and TSV-free Monolithic 3D-IC with Heterogeneous Integration of Logic Memory and Sensor Analogy Circuitry for Internet of Things”, International Electron Devices Meeting (IEDM)2015, Washington DC, USA
  6. Kai-Shin Li, Pin-Guang Chen, Tung-Yan Lai, Chang-Hsien Lin, Cheng-Chih Cheng, Chun-Chi Chen, Yun-Jie Wei, Yun-Fang Hou, Ming-Han Liao, Min-Hung Lee, Min-Cheng Chen, Jia-Min Sheih, Wen-Kuan Yeh, Fu-Liang Yang, “Sub-60mV-Swing Negative-Capacitance FinFET without Hysteresis”, International Electron Devices Meeting (IEDM)2015, Washington DC, USA
  7. Chih-Chao Yang, Jia-Min Shieh*, Tung-Ying Hsieh, Wen-Hsien Huang, Hsing-Hsiang Wang, Chang-Hong Shen, Tsung-Ta Wu, Yun-Fang Hou, Yi-Ju Chen, Yao-Jen Lee, Min-Cheng Chen, Fu-Liang Yang, Yu-Hsiu Chen, Meng-Chyi Wu, and Wen-Kuan Yeh, Sayeef Salahuddin, Chenming Hu, “Enabling Low Power BEOL Compatible monolithic 3D+ nanoelectronics for IoTs Using Local and Selective Far-Infrared Ray Laser Anneal Technology” International Electron Devices Meeting (IEDM)2015, Washington DC, USA
  8. Chang-Hong Shen, Jia-Min Shieh, Wen-Hsien Huang, Tsung-Ta Wu, Chien-Fu Chen, Ming-Hsuan Kao, Chih-Chao Yang, Chein-Din Lin1, Hsing-Hsiang Wang, Tung-Ying Hsieh, Bo-Yuan Chen, Guo-Wei Huang, Meng-Fan Chang, and Fu-Liang Yang, “Heterogeneously integrated sub-40nm low-power epi-like Ge/Si monolithic 3D-IC with stacked SiGeC ambient light harvester”, IEDM 2014, San Francisco, USA
  9. Chih-Chao Yang, Jia-Min Shieh1*, Tung-Ying Hsieh, Wen-Hsien Huang, Hsing-Hsiang Wang, Chang-Hong Shen, Tsung-Ta Wu, Chun-Yuan Chen, Kuei-Shu Chang-Liao, Jung-Hau Shiu, Meng-Chyi Wu, and Fu-Liang Yang, “Vth adjustable self-aligned embedded source/drain Si/Ge nanowire FETs and dopant-free NVMs for 3D sequentially integrated circuit”, IEDM 2014, San Francisco, USA
  10. Min-Cheng Chen, Chia-Yi Lin, Kai-Hsin Li, Lain-Jong Li, Chang-Hsiao Chen, Cheng-Hao Chuang, Ming-Dao Lee, Yi-Ju Chen, Yun-Fang Hou, Chang-Hsien Lin, Chun-Chi Chen, Bo-Wei Wu, Cheng-San Wu, Ivy Yang, Yao-Jen Lee, Wen-Kuan Yeh, Tahui Wang, Fu-Liang Yang and Chenming Hu, “Hybrid Si/TMD 2D Electronic Double Channels Fabricated Using Solid CVD Few-Layer-MoS2 Stacking for Vth Matching and CMOS-Compatible 3DFETs”, IEDM 2014, San Francisco, USA
  11. Kai-Shin Li, ChiaHua Ho, Ming-Taou Lee, Min-Cheng Chen, Cho-Lun Hsu, J. M. Lu, C. H. Lin, C. C. Chen, B. W. Wu, Y. F. Hou, C. Y. Lin, Y. J. Chen, T. Y. Lai, M. Y. Li, I. Yang, C. S. Wu, and Fu-Liang Yang “Utilizing Sub-5 nm Sidewall Electrode Technology for Atomic-Scale Resistive Memory Fabrication” , IEEE Symposium on VLSI Technology (VLSI Technology), pp. 164-165, 2014
  12. I-Fang Cheng, Hsien-Chang Chang, Tzu-Ying Chen, Chenming Hu, and Fu-Liang Yang, “Rapid (<5min) Identification of Pathogen in Human Blood by Electrokinetic Concentration and Surface-Enhanced Raman Spectroscopy”, Scientific Reports, 6 August 2013.
  13. M.C. Chen, C.Y. Lin, B.Y. Chen, C.H. Lin, G.W. Huang, ChiaHua Ho, Tahui Wang, Chenming Hu, and F.L. Yang, “Random Telegraph Noise in 1X nm CMOS Silicide Contacts and a Method to Extract Trap Density”, IEEE Electron Device Letters (EDL) , pp.591-593, 2012.
  14. Wen-Hsien Huang, Jia-Min Shieh*, Fu-Ming Pan, Chang-Hong Shen, Yu-Chung Lien,Min-An Tsai, Hao-Chung Kuo, Bau-Tong Dai, and Fu-Liang Yang," UV–Visible Light-Trapping Structure of LooselyPacked Submicrometer Silica Sphere for Amorphous Silicon Solar Cells", IEEE Electron Device Letters(EDL), 33, 1036(2012).
  15. Yu-Chung Lien, Jia-Min Shieh*, Wen-Hsien Huang, Cheng-Hui Tu, Chieh Wang, Chang-Hong Shen, Bau-Tong Dai, Ci-Ling Pan, Chenming Hu, and Fu-Liang Yang, "Fast programming metal-gate Si quantum dot nonvolatile memory using green nanosecond laser spike annealing", APPLIED PHYSICS LETTERS 100, 143501 (2012). (Research Highlights)
  16. M.C. Chen, H.Y. Chen, C.Y. Lin, C.H. Chien, T.F. Hsieh, J.T. Horng, J.T. Qiu, C.C. Huang, C.H. Ho and F.L. Yang, ”A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications”, Sensors, pp.3952-3963, 2012.
  17. Hou-Yu Chen; Chun-Chi Chen; Fu-Kuo Hsueh; Jan-Tsai Liu; Shyi-Long Shy; Cheng-San Wu; Chao-Hsin Chien; Chenming Hu; Chien-Chao Huang; Fu-Liang Yang “A Novel Nanoinjection Lithography (NInL) Technology and Its Application for 16-nm Node Device Fabrication”, IEEE TRANSACTIONS ON ELECTRON DEVICES, V. 58-11: 3678 - 3686 NOV 2011.
  18. Chang-Hong Shen, Jia-Min Shieh, Jung Y. Huang, Hao-Chung Kuo, Chih-Wei Hsu, Bau-Tong Dai, Ching-Ting Lee, Ci-Ling Pan, and Fu-Liang Yang “Inductively coupled plasma deposited semiconductor films for low cost high-efficiency solar cells with high light-soaking stability” , APPLIED PHYSICS LETTERS, 99, 033510 (2011)
  19. Jia-Min Shieh, Wen-Chien Yu, Jung Y. Huang, Chao-Kei Wang, Bau-Tong Dai,Huang-Yan Jhan, Chih-Wei Hsu, Hao-Chung Kuo, Fu-Liang Yang, and Ci-Ling Pan ”Near-infrared silicon quantum dots metal-oxide-semiconductor field-effect transistor photodetector” APPLIED PHYSICS LETTERS 94, 241108 (2009) .
  20. Couthored a Chapter “Overview of Metal-Oxide Resistive Memory”, in “NONVOLATILE MEMORIES, Materials, Devices and Applications”, ChiaHua Ho and Fu-Liang Yang, edited by Tseung-Yuen Tseng and Simon M. Sze, AMERICAN SCIENTIFIC PUBLISHERS, 2012
  21. Guang-Li Luo, Shih-Chiang Huang, Cheng-Ting Chung, Dawei Heh1, Chao-Hsin Chien, Chao-Ching Cheng, Yao-Jen Lee, Wen-Fa Wu, Chiung-Chih Hsu, Mei-Ling Kuo, Jay-Yi Yao, Mao-Nan Chang, Chee-Wee Liu, Chenming Hu, Chun-Yen Chang, and Fu-Liang Yang, “A Comprehensive Study of Ge1-xSix on Ge for the Ge nMOSFETs with Tensile Stress, Shallow Junctions and Reduced Leakage”, IEDM Dec.2009
  22. Yao-Jen Lee, Yu-Lun Lu, Fu-Kuo Hsueh, Kuo-Chin Huang, Chia-Chen Wan, Tz-Yen Cheng, Ming-Hung Han, Jeff M. Kowalski, Jeff E. Kowalski, Dawei Heh, Hsi-Ta Chuang, Yiming Li, Tien-Sheng Chao, Ching-Yi Wu, and Fu-Liang Yang, “3D 65nm CMOS with 320°C Microwave Dopant Activation”, IEDM Dec.2009
  23. Chen, HM (Chen, Hung-Ming); Hwang, JR (Hwang, Jiunn-Ren); Li, Y (Li, Yiming); Yang, FL (Yang, Fu-Liang) “Novel strained CMOS devices with STI stress buffer layers”, 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Proceedings of Technical Papers Pages: 80-81 DOI: 10.1109/ISPACS.2007.4445828, published 2007
    [ DOI:10.1109/ISPACS.2007.4445828 ]
  24. Li, YM (Li, Yiming)1; Hwang, CH (Hwang, Chih-Hong)1; Yu, SM (Yu, Shao-Ming); Huang, HM (Huang, Hsuan-Ming)1; Yeh, TC (Yeh, Ta-Ching)1; Cheng, HW (Cheng, Hui-Wen)1; Chen, HM (Chen, Hung-Ming); Hwang, JR (Hwang, Jiunn-Ren); Yang, FL (Yang, Fu-Liang) “Characteristic fluctuation dependence on discrete dopant for 16nm SOI FinFETs at different temperature”, SISPAD 2007: SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES 2007(TU Wien, Vienna, AUSTRIA) Pages: 365-368 DOI: 10.1007/978-3-211-72861-1_88 Published: 2007
    [ DOI:10.1007/978-3-211-72861-1_88 ]
  25. Fu-Liang Yang, Jiunn-Ren Hwang, Hung-Ming Chen, Jeng-Jung Shen,.., and Denny D. Tang, “Discrete Dopant Fluctuated 20nm/15nm-Gate Planar CMOS”, Symp. VLSI Tech., 2007. (Kyoto, Japan)
  26. Dunga, MV (Dunga, Mohan V.); Lin, CH (Lin, Chung-Hsun); Lu, DD (Lu, Darsen D.); Xiong, W (Xiong, Weize); Cleavelin, CR (Cleavelin, C. R.); Patruno, P (Patruno, P.); Hwang, JR (Hwang, Jiunn-Ren); Yang, FL (Yang, Fu-Liang); Niknejad, AM (Niknejad, Ali M.); Hu, C (Hul, Chenming) “BSIM-MG: A versatile multi-gate FET model for mixed-signal design”, 2007 Symposium on VLSI Technology, (Kyoto, JAPAN) Digest of Technical Papers Pages: 60-61 DOI: 10.1109/VLSIT.2007.4339727 Published: 2007
    [ DOI:10.1109/VLSIT.2007.4339727 ]
  27. Yang, FL (Yang, Fu-Liang); Hwang, JR (Hwang, Jiunn-Ren); Li, YM (Li, Yiming) ”Electrical characteristic fluctuations in sub-45nm CMOS devices”, PROCEEDINGS OF THE IEEE 2006 CUSTOM INTEGRATED CIRCUITS CONFERENCE Book Series: IEEE Custom Integrated Circuits Conference Pages: 691-694 DOI: 10.1109/CICC.2006.320881 Published: 2006
    [ DOI:10.1109/CICC.2006.320881 ]
  28. Jiunn-Ren Hwang, Tsung-Lin Lee, Huan-Chi Ma*, Tzyh-Cheang Lee,…, and Fu-Liang Yang,“20nm Gate Bulk-FinFET SONOS Flash”, IEDM, 2005. (Washington DC, USA)
  29. Hou-Yu Chen, Chang-Yun Chang, Chien-Chao Huang, T.-X. Chung, . ., and Fu-Liang Yang, “Novel 20nm Hybrid SOI/Bulk CMOS Technology with 0.183m2 6T-SRAM Cell by Immersion Lithography”, Symp. VLSI Tech., 2005. (Kyoto, Japan)
  30. Fu-Liang Yang, Di.-Hong. Lee, H.-Y. Chen, C.-Y. Chang, S.-D. Liu,.. , and Chenming Hu , “5nm-Gate Nanowire FinFET” Symp. VLSI Tech., 2004. (Honolulo, USA)
  31. Fu-Liang Yang, Hou-Yu Chen, C.-C. Huang, T.-X. Chung, C.-Y. Chang,.., and Chenming Hu , “A 45nm Node SOI Technology with 0.296m2 6T-SRAM Cell”. Symp. VLSI Tech., 2004. (Honolulo, USA)
  32. Fu-Liang Yang, Di.-Hong. Lee, H.-Y. Chen, C.-Y. Chang, S.-D. Liu,.. , and Chenming Hu, “A 65nm Node Strained SOI Technology with Slim Spacer”, IEDM, 2003. (Washington DC, USA)
  33. Fu-Liang Yang, Hou-Yu Chen, C.-C. Huang, C.-H. Ge, K.-W. Su,…, and Chenming Hu, “Strained FIP-SOI (FinFET/FD/PD-SOI) for Sub-65nm CMOS Scaling”, Symp. VLSI Tech., 2003. (Kyoto, Japan)
  34. Fu-Liang Yang, Hao-Yu Chen, F.-C. Chen, C.-C. Huang, C.-Y. Chang,..., and Chenming Hu, “25nm CMOS Omega FETs”, IEDM, 2002. (San Francisco, USA)
  35. Fu-Liang Yang, Haur-Ywh Chen, F.-C. Chen, Y.-L. Chan, K.-N. Yang,.., and Chenming Hu, “35nm CMOS FinFETs”, Symp. VLSI Tech., 2002. (Honolulo, USA)
  36. K. N. Yang, Yi-Lin Chan, Yu-Lin Chu, Hou-Yu Chen, Fu-Liang Yang, and Chenming Hu, “High Performance 0.1 m PD SOI Tunneling-Biased MOSFETs (TB-MOS)”, IEDM, 2001 (Late News paper)


  1. Totally 242 patents, 135 USA patents (including authored and co-authored).